The invention relates to a computer system and a method of operating such in which an address and data path distributes bit packets between a CPU and other on-chip modules.
Computer systems may incorporate a CPU with other on-chip modules including a memory interface such that a plurality of interconnected devices need to intercommunicate. Some signals may be generated in response to-a hardware occurrence and other signals may be in response to a software operation.
An object of the present invention is to provide an improved computer system and method of operating a computer system arranged to handle interdevice communications which are either hardware of software generated.
The invention provides a method of operating a computer system which method comprises interconnecting on a chip a plurality of devices including at least one CPU with a plurality of addressable modules including a memory interface, and at least one external communication port, the interconnection being provided by an address and data path, the method further comprising using said address and data path to distribute between devices in the system bit packets comprising memory access packets, event request packets to provide prioritised interrupts for operation of said CPU and control packets to provide control commands to the CPU, said packets being formed selectively in response to both software and hardware circuitry, the packet format being a common format providing a destination address and a function decodable at the destination device.
Preferably said CPU is operated to execute instructions selected from an instruction set of the computer system to generate packets of said common format and distribute such packets on the address and data path.
Said CPU is operated to execute an instruction to generate a control packet providing a control command for a device indicated by the destination address of the packet.
Said CPU is operated to execute a selected instruction to generate an event request packet providing a prioritised interrupt for use at a destination indicated by the destination address in the packet.
Said CPU is operated to execute a selected instruction to generate a packet forming a memory read or write request at a destination address indicated in the packet.
Preferably packet generating circuitry in at least one of said on-chip devices detects an event, generates a bit packet in accordance with the event detected, provides a destination address in the bit packet and distributes the bit packet on said address and data bus.
Said circuitry may generate an interrupt request packet and include a priority indicator in the request packet for use by the destination device.
Said circuitry may detect an event requiring generation of a control packet and in response thereto generate a control packet with a destination address and a destination device responds to the control command on receipt of the packet.
Preferably the packet format includes an indication of the destination address of the packet, an indicator of the function of the packet and an indication of the source address of the packet.
Preferably each request packet includes a packet number indicator for the packet, each response packet including a number indicator corresponding to the request packet whereby each response packet can be matched to the request packet on the turn of the response packet to the source of the request packet.
The invention also provides a computer system comprising an integrated circuit device with an address and data path for distributing addressed bit packets and interconnecting a plurality of on-chip devices including at least one CPU, at least one other addressable module and a memory interface, said module having packet generating circuitry responsive to an event to generate either an event request packet including a destination address or a control packet to provide control commands to a destination address, said CPU including an instruction set operable to execute instructions generating event request packets, memory access packets or control packets, said CPU further comprising packet generating circuitry to generate packets for distribution of the address and data path having a common format with packets generated by said module.